High Performance and Endurance Non-volatile Memory Based Storage Systems

ABSTRACT

High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge, while the page buffers are configured to hold data to be transmitted between the host computer and the at least one NVM device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part (CIP) of U.S. patentapplication for “High Integration of Intelligent Non-Volatile MemoryDevices”, Ser. No. 12/054,310, filed Mar. 24, 2008, which is a CIP of“High Endurance Non-Volatile Memory Devices”, Ser. No. 12/035,398, filedFeb. 21, 2008, which is a CIP of “High Speed Controller for Phase ChangeMemory Peripheral Devices”, U.S. application Ser. No. 11/770,642, filedon Jun. 28, 2007, which is a CIP of “Local Bank Write Buffers forAcceleration a Phase Change Memory”, U.S. application Ser. No.11/748,595, filed May 15, 2007, which is CIP of “Flash Memory Systemwith a High Speed Flash Controller”, application Ser. No. 10/818,653,filed Apr. 5, 2004, now U.S. Pat. No. 7,243,185.

This application is also a CIP of U.S. patent application for“Intelligent Solid-State Non-Volatile Memory Device (NVMD) System withMulti-Level Caching of Multiple Channels”, Ser. No. 12/115,128, filed onMay 5, 2008.

This application is also a CIP of U.S. patent application for “HighPerformance Flash Memory Devices”, Ser. No. 12/017,249, filed on Feb.27, 2008.

This application is also a CIP of U.S. patent application for “Methodand Systems of Managing Memory Addresses in a Large Capacity Multi-LevelCell (MLC) based Memory Device”, Ser. No. 12/025,706, filed on Feb. 4,2008, which is a CIP application of “Flash Module with Plane-interleavedSequential Writes to Restricted-Write Flash Chips”, Ser. No. 11/871,011,filed Oct. 11, 2007.

This application is also a CIP of U.S. patent application for“Single-Chip Multi-Media Card/Secure Digital controller Reading Power-onBoot Code from Integrated Flash Memory for User Storage”, Ser. No.12/128,916, filed on May 29, 2008, which is a continuation of U.S.patent application for the same title, Ser. No. 11/309,594, filed onAug. 28, 2006, now issued as U.S. Pat. No. 7,383,362 on Jun. 3, 2008,which is a CIP of U.S. patent application for “Single-Chip USBController Reading Power-On Boot Code from Integrated Flash Memory forUser Storage”, Ser. No. 10/707,277, filed on Dec. 2, 2003, now issued asU.S. Pat. No. 7,103,684.

This application is also a CIP of U.S. patent application for“Electronic Data Flash Card with Fingerprint Verification Capability”,Ser. No. 11/458,987, filed Jul. 20, 2006, which is a CIP of U.S. patentapplication for “Highly Integrated Mass Storage Device with anIntelligent Flash Controller”, Ser. No. 10/761,853, filed Jan. 20, 2004,now abandoned.

This application is also a CIP of U.S. patent application for “flashmemory devices with security features”, Ser. No. 12/099,421, filed onApr. 8, 2008.

This application is also a CIP of U.S. patent application for“Electronic Data Storage Medium with Fingerprint VerificationCapability”, Ser. No. 11/624,667, filed on Jan. 18, 2007, which is adivisional of U.S. patent application Ser. No. 09/478,720, filed on Jan.6, 2000, now U.S. Pat. No. 7,257,714 issued on Aug. 14, 2007.

This application may be related to a U.S. Pat. No. 7,073,010 for “USBSmart Switch with Packet Re-Ordering for Interleaving among MultipleFlash-Memory Endpoints Aggregated as a Single Virtual USB Endpoint”issued on Jul. 4, 2006.

FIELD OF THE INVENTION

The invention relates to data storage using non-volatile memory (NVM),more particularly to high performance and endurance NVM based storagesystems.

BACKGROUND OF THE INVENTION

Traditionally, hard disk drives have been used as data storage in acomputing device. With advance of non-volatile memory (e.g., NAND flashmemory), some attempts have been made to use non-volatile memory as thedata storage.

Advantages of using NAND flash memory as data storage over hard diskdrive are as follows:

-   (1) No moving parts;-   (2) No noise or vibration caused by the moving parts;-   (3) Higher shock resistance;-   (4) Faster startup (i.e., no need to wait for spin-up to steady    state);-   (5) Faster random access;-   (6) Faster boot and application launch time; and-   (7) Lower read and write latency (i.e., seek time).

However, there are shortcomings of using non-volatile memory as datastorage. First problem is related to performance, NAND flash memory canonly be accessed (i.e., read and/or programmed(written)) in data chunks(e.g., 512-byte data sector) instead of bytes. In addition, NAND flashmemory needs to be erased before any new data can be written into, anddata erasure operations can only be carried out in data blocks (e.g.,128 k-byte, 256 k-byte, etc.). All of the valid data in a data blockmust be copied to a new allocated block before any erasure operationthereby causing performance slow down. The characteristics of dataprogramming and erasure not only makes NAND flash memory cumbersome tocontrol (i.e., requiring a complex controller and associated firmware),but also difficult to realize the advantage of higher accessing speedover the hard disk drive (e.g., frequent out-of sequence updating in afile may result into many repeated data copy/erasure operations).

Another problem in NAND flash memory relates to endurance. Unlike harddisk drives, NAND flash memories have a life span measuring by limitednumber of erasure/programming cycles. As a result, one key goal of usingNAND flash memories as data storage to replace hard disk drives is toavoid data erasure/programming as much as possible.

It would be desirable, therefore, to have an improved non-volatilememory based storage system that can overcome shortcomings describedherein.

BRIEF SUMMARY OF THE INVENTION

This section is for the purpose of summarizing some aspects of thepresent invention and to briefly introduce some preferred embodiments.Simplifications or omissions in this section as well as in the abstractand the title herein may be made to avoid obscuring the purpose of thesection. Such simplifications or omissions are not intended to limit thescope of the present invention.

High performance and endurance non-volatile memory (NVM) based storagesystems are disclosed. According to one aspect of the present invention,a NVM based storage system comprises at least one intelligent NVMdevice, an internal bus, at least one intelligent NVM device controller,a hub timing controller, a central processing unit, a data dispatcherand a storage protocol interface bridge. The intelligent NVM deviceincludes a control interface logic and NVM. The control interface logicis configured to receive commands, logical addresses, data and timingsignals from corresponding one of the at least one intelligent NVMdevice controller. Logical-to-physical address conversion can beperformed within the control interface logic, thereby eliminating theneed of address conversion in a storage system level controller (e.g.,NVM based storage system). This feature also enables distributed addressmappings instead of centralized prior art approaches. The datadispatcher together with the hub timing controller is configured fordispatching commands and sending relevant timing clock cycle to each ofthe at least one NVM device controller via the internal bus to enableinterleaved parallel data transfer operations. The storage protocolinterface bridge is configured for receiving data transfer commands froma host computer system via an external storage interface. An intelligentNVM device can be implemented as a single chip, which may include, butnot be limited to, a product-in-package, a device-on-device package, adevice-on-silicon package, or a multi-die package.

According to another aspect of the present invention, a volatile memorybuffer together with corresponding volatile memory controller andphase-locked loop (PLL) circuit is also included in a NVM based storagesystem. The volatile memory buffer is partitioned to two parts: acommand queue and one or more page buffers. The command queue isconfigured to hold received data transfer commands received by thestorage protocol interface bridge, while the page buffers are configuredto hold transition data to be transmitted between the host computer andthe at least one NVM device. PLL circuit is configured for providingtiming clock to the volatile memory buffer.

According to yet another aspect of the present invention, the volatilememory buffer allows data write commands with overlapped target addressto be merged in the volatile memory buffer before writing to the atleast one NVM device, thereby reducing repeated data programming orwriting into same area of the NVM device. As a result, endurance of theNVM based storage system is increased due to less numbers of dataprogramming.

According to yet another aspect, the volatile memory buffer allowspreloading of data to anticipate requested data in certain data readcommands hence increasing performance of the NVM based storage system.

According to yet another aspect, when a volatile memory buffer isincluded in a NVM based storage system, the system needs to monitorunexpected power failure. Upon detecting such power failure, the storedcommands in the command queue along with the data in the page buffersmust be stored in a special location using reserved electric energystored in a designated capacitor. The special location is a reservedarea of the NVM device, for example, the last physical block of the NVMdevice. The command queue is so sized that limited amount of electricenergy stored in the designated capacitor can be used for copying all ofthe stored data to the reserved area. In order to further maximize thecapacity of the command queue, emergency data dump is performed withoutaddress conversion.

According to still another aspect, after unexpected power failure, a NVMbased storage system can restore its volatile memory buffer by copyingthe data from the reserved area of the NVM to the volatile memorybuffer.

Other objects, features, and advantages of the present invention willbecome apparent upon examining the following detailed description of anembodiment thereof, taken in conjunction with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the presentinvention will be better understood with regard to the followingdescription, appended claims, and accompanying drawings as follows:

FIG. 1A is a block diagram showing salient components of a first flashmemory device (with fingerprint verification capability), in which anembodiment of the present invention may be implemented;

FIG. 1B is a block diagram showing salient components of a second flashmemory device (without fingerprint verification capability), in which anembodiment of the present invention may be implemented;

FIG. 1C is a block diagram showing salient components of a flash memorysystem embedded on a motherboard, in which an embodiment of the presentinvention may be implemented;

FIG. 1D is a block diagram showing salient components of a flash memorymodule coupling to a motherboard, in which an embodiment of the presentinvention may be implemented;

FIG. 1E is a block diagram showing salient components of a flash memorymodule without a controller, the flash memory module couples to amotherboard, in which an embodiment of the present invention may beimplemented;

FIG. 2A is a block diagram depicting salient components of a firstexemplary non-volatile memory (NVM) based storage system, according oneembodiment of the present invention;

FIG. 2B is a block diagram depicting salient components of a secondexemplary NVM based storage system, according one embodiment of thepresent invention;

FIG. 2C is a block diagram depicting salient components of a thirdexemplary NVM based storage system, according one embodiment of thepresent invention;

FIG. 2D is a block diagram depicting salient components of a fourthexemplary NVM based storage system, according one embodiment of thepresent invention;

FIG. 2E-1 is a block diagram showing exemplary block access interfacesignals used in the NVM based storage system of FIG. 2A

FIG. 2E-2 is a block diagram showing exemplary synchronous DDR interlocksignals used in the NVM based storage system of FIG. 2B;

FIG. 2F is a functional block diagram showing the exemplary DDR channelcontroller in the NVM based storage system of FIG. 2B;

FIG. 2G is a functional block diagram showing the exemplary DDR controlinterface and NVM in the NVM based storage system of FIG. 2B;

FIG. 2H is a flowchart illustrating an exemplary process of encryptingplain text data using an data encryption/decryption engine based on128-bit Advanced Encryption Standard (AES) in accordance with oneembodiment of the present invention;

FIG. 3 is a block diagram illustrating salient components of anexemplary dual-mode NVM based storage device;

FIG. 4A is a diagram showing an exemplary intelligent non-volatilememory device controller for single channel intelligent NVMD array inaccordance with one embodiment of the present invention;

FIG. 4B is a diagram showing an exemplary intelligent non-volatilememory device controller for multiple channel interleaved intelligentNVMD array in accordance with one embodiment of the present invention;

FIG. 5A is a block diagram showing data structure of host logicaladdress, NVM physical address and volatile memory buffer, according toone embodiment of the present invention;

FIG. 5B is a block diagram showing data structure used in intelligentNVMD of FIG. 2B, according to an embodiment of the present invention;

FIG. 5C is a block diagram showing exemplary data structure of commandqueue and a page buffer configured in volatile memory buffer, accordingto an embodiment of the present invention;

FIG. 6A is a timeline showing time required for writing one page of datato NVM in a NVM based storage system without a volatile memory buffersupport;

FIG. 6B is a timeline showing time required for writing one page of datato NVM in a NVM based storage system without a volatile memory buffersupport, when a bad block is encountered;

FIG. 6C is a timeline showing time required for performing burst writeto a volatile memory buffer and then to an intelligent NVM device whencommand queue is full under normal operation;

FIG. 6D is a timeline showing time required for performing burst writeto a volatile memory buffer and then to an intelligent NVM device afterunexpected power failure has been detected;

FIGS. 7A-B collectively are a flowchart illustrating an exemplaryprocess of performing data transfer in the NVM based storage system ofFIG. 2B, according to an embodiment of the present invention;

FIG. 8 is a flowchart illustrating an exemplary process of using avolatile memory buffer in the NVM based storage system of FIG. 2B,according to another embodiment of the present invention;

FIG. 9 is a flowchart illustrating an exemplary process of performingdirect memory access operation in the NVM based storage system of FIG.2B, according to an embodiment of the present invention;

FIG. 10 is a flowchart illustrating a first exemplary process afterunexpected power failure has been detected in the NVM based storagesystem of FIG. 2B, according to an embodiment of the present invention;

FIG. 11 is a flowchart illustrating a second exemplary process afterdetecting an unexpected power failure in the NVM based storage system ofFIG. 2B, according to an embodiment of the present invention;

FIG. 12 is a flowchart illustrating an exemplary process of restoringvolatile memory buffer of the NVM based storage system of FIG. 2B afteran unexpected power failure, according to an embodiment of the presentinvention;

FIG. 13A is a waveform diagram showing time required for performing datawrite operation from the volatile memory buffer to the intelligent NVMdevice in the NVM based storage system of FIG. 2A; and

FIG. 13B is a waveform diagram showing time required for performing datawrite operation from the volatile memory (i.e., double data ratesynchronous dynamic random access memory) buffer to the intelligent NVMdevice in the NVM based storage system of FIG. 2B.

DETAILED DESCRIPTION

In the following description, numerous details are set forth to providea more thorough explanation of embodiments of the present invention. Itwill be apparent, however, to one skilled in the art, that embodimentsof the present invention may be practiced without these specificdetails. In other instances, well-known structures and devices are shownin block diagram form, rather than in detail, in order to avoidobscuring embodiments of the present invention.

Reference herein to “one embodiment” or “an embodiment” means that aparticular feature, structure, or characteristic described in connectionwith the embodiment can be included in at least one embodiment of theinvention. The appearances of the phrase “in one embodiment” in variousplaces in the specification are not necessarily all referring to thesame embodiment, nor are separate or alternative embodiments mutuallyexclusive of other embodiments. Further, the order of blocks in processflowcharts or diagrams representing one or more embodiments of theinvention do not inherently indicate any particular order nor imply anylimitations in the invention.

Embodiments of the present invention are discussed herein with referenceto FIGS. 1A-13B. However, those skilled in the art will readilyappreciate that the detailed description given herein with respect tothese figures is for explanatory purposes as the invention extendsbeyond these limited embodiments.

FIG. 1A is a block diagram illustrating salient components of a firstflash memory device (with fingerprint verification capability), in whichan embodiment of the present invention may be implemented. The firstflash memory device is adapted to a motherboard 109 via an interface bus113. The first flash memory device includes a card body 100, aprocessing unit 102, memory device 103, a fingerprint sensor 104, aninput/output (I/O) interface circuit 105, an optional display unit 106,an optional power source (e.g., battery) 107, and an optional functionkey set 108. The motherboard 109 may be a motherboard of a desktopcomputer, a laptop computer, a mother board of a personal computer, acellular phone, a digital camera, a digital camcorder, a personalmultimedia player or any other computing or electronic devices.

The card body 100 is configured for providing electrical and mechanicalconnection for the processing unit 102, the memory device 103, the I/Ointerface circuit 105, and all of the optional components. The card body100 may comprise a printed circuit board (PCB) or an equivalentsubstrate such that all of the components as integrated circuits may bemounted thereon. The substrate may be manufactured using surface mounttechnology (SMT) or chip on board (COB) technology.

The processing unit 102 and the I/O interface circuit 105 arecollectively configured to provide various control functions (e.g., dataread, write and erase transactions) of the memory device 103. Theprocessing unit 102 may also be a standalone microprocessor ormicrocontroller, for example, an 8051, 8052, or 80286 Intel®microprocessor, or ARM®, MIPS® or other equivalent digital signalprocessor. The processing unit 102 and the I/O interface circuit 105 maybe made in a single integrated circuit, for application specificintegrated circuit (ASIC).

The memory device 103 may comprise one or more non-volatile memory(e.g., flash memory) chips or integrated circuits. The flash memorychips may be single-level cell (SLC) or multi-level cell (MLC) based. InSLC flash memory, each cell holds one bit of information, while morethan one bit (e.g., 2, 4 or more bits) are stored in a MLC flash memorycell. A detail data structure of an exemplary flash memory is describedand shown in FIG. 4A and corresponding descriptions thereof.

The fingerprint sensor 104 is mounted on the card body 100, and isadapted to scan a fingerprint of a user of the first electronic flashmemory device 100 to generate fingerprint scan data. Details of thefingerprint sensor 104 are shown and described in a co-inventor's U.S.Pat. No. 7,257,714, entitled “Electronic Data Storage Medium withFingerprint Verification Capability” issued on Aug. 14, 2007, the entirecontent of which is incorporated herein by reference.

The memory device 103 stores, in a known manner therein, one or moredata files, a reference password, and the fingerprint reference dataobtained by scanning a fingerprint of one or more authorized users ofthe first flash memory device. Only authorized users can access thestored data files. The data file can be a picture file, a text file orany other file. Since the electronic data storage compares fingerprintscan data obtained by scanning a fingerprint of a user of the devicewith the fingerprint reference data in the memory device to verify ifthe user is the assigned user, the electronic data storage can only beused by the assigned user so as to reduce the risks involved when theelectronic data storage is stolen or misplaced.

The input/output interface circuit 105 is mounted on the card body 100,and can be activated so as to establish communication with themotherboard 109 by way of an appropriate socket via an interface bus113. The input/output interface circuit 105 may include circuits andcontrol logic associated with a Universal Serial Bus (USB) interfacestructure that is connectable to an associated socket connected to ormounted on the motherboard 109. The input/output interface circuit 105may also be other interfaces including, but not limited to, SecureDigital (SD) interface circuit, Micro SD interface circuit, Multi-MediaCard (MMC) interface circuit, Compact Flash (CF) interface circuit,Memory Stick (MS) interface circuit, PCI-Express interface circuit, aIntegrated Drive Electronics (IDE) interface circuit, Serial AdvancedTechnology Attachment (SATA) interface circuit, external SATA, RadioFrequency Identification (RFID) interface circuit, fiber channelinterface circuit, optical connection interface circuit.

The processing unit 102 is controlled by a software program module(e.g., a firmware (FW)), which may be stored partially in a ROM (notshown) such that processing unit 102 is operable selectively in: (1) adata programming or write mode, where the processing unit 102 activatesthe input/output interface circuit 105 to receive data from themotherboard 109 and/or the fingerprint reference data from fingerprintsensor 104 under the control of the motherboard 109, and store the dataand/or the fingerprint reference data in the memory device 103; (2) adata retrieving or read mode, where the processing unit 102 activatesthe input/output interface circuit 105 to transmit data stored in thememory device 103 to the motherboard 109; or (3) a data resetting orerasing mode, where data in stale data blocks are erased or reset fromthe memory device 103. In operation, motherboard 109 sends write andread data transfer requests to the first flash memory device 100 via theinterface bus 113, then the input/output interface circuit 105 to theprocessing unit 102, which in turn utilizes a flash memory controller(not shown or embedded in the processing unit) to read from or write tothe associated at least one memory device 103. In one embodiment, forfurther security protection, the processing unit 102 automaticallyinitiates an operation of the data resetting mode upon detecting apredefined time period has elapsed since the last authorized access ofthe data stored in the memory device 103.

The optional power source 107 is mounted on the card body 100, and isconnected to the processing unit 102 and other associated units on cardbody 100 for supplying electrical power (to all card functions) thereto.The optional function key set 108, which is also mounted on the cardbody 100, is connected to the processing unit 102, and is operable so asto initiate operation of processing unit 102 in a selected one of theprogramming, data retrieving and data resetting modes. The function keyset 108 may be operable to provide an input password to the processingunit 102. The processing unit 102 compares the input password with thereference password stored in the memory device 103, and initiatesauthorized operation of the first flash memory device 100 upon verifyingthat the input password corresponds with the reference password. Theoptional display unit 106 is mounted on the card body 100, and isconnected to and controlled by the processing unit 102 for displayingdata exchanged with the motherboard 109.

A second flash memory device (without fingerprint verificationcapability) is shown in FIG. 1B. The second flash memory device includesa card body 120 with a processing unit 102, an I/O interface circuit 105and at least one flash memory chip 123 mounted thereon. Similar to thefirst flash memory device, the second flash memory device couples to amotherboard or a host computing system 109 via an interface bus 113.Fingerprint functions such as scanning and verification may be handledby the host system 109.

FIG. 1C shows a flash memory system 140 integrated with a motherboard160. Substantially similar to the second flash memory device 120 forFIG. 1B, the flash system 140 contains a processing unit 102, an I/Ointerface circuit 105 and at least one flash memory chip 123. Includedon the motherboard 160, there is a host system 129 and the flash system140. Data, command and control signals for the flash system 140 aretransmitted through an internal bus.

FIG. 1D shows a flash memory module 170 coupling to a motherboard 180.The flash memory module 170 comprises a processing unit 102 (e.g., aflash controller), one or more flash memory chips 123 and an I/Ointerface circuit 105. The motherboard 180 comprises a core system 178that may include CPU and other chip sets. The connection between themotherboard and the flash memory module 170 is through an internal bussuch as a Peripheral Component Interconnect Express (PCI-E).

Another flash memory module 171 is shown in FIG. 1E. The device 171comprised only flash memory chips or integrated circuits 123. Processingunit 102 (e.g., a flash memory controller) and I/O interface circuit 105are built onto a motherboard 180 along with a core system 178 (i.e., aCPU and other chip sets). In a slight alternative embodiment, theprocessing unit 102 may be included in the CPU of the core system 178.

Referring now to FIG. 2A, which is a block diagram depicting a firstexemplary non-volatile memory (NVM) based storage system 210 a,according to an embodiment of the present invention. The first NVM basedstorage system 210 a comprises at least one intelligent NVM device 237,an internal bus 230, at least one intelligent NVM device controller 231,a volatile memory buffer 220, a volatile memory buffer controller 222, ahub timing controller 224, a local central processing unit (CPU) 226, aphase-locked loop (PLL) circuit 228, a storage protocol interface bridge214 and a data dispatcher 215.

Each of the at least one intelligent NVM device 237 includes a controlinterface (CTL IF) 238 and a NVM 239. The control interface 238 isconfigured for communicating with corresponding intelligent NVM devicecontroller 231 via NVM interface 235 for logical addresses, commands,data and timing signals. The control interface 238 is also configuredfor extracting a logical block address (LBA) from each of the receivedlogical addresses such that corresponding physical block address (PBA)is determined within the intelligent NVM device 237. Furthermore, thecontrol interface 238 is configured for managing wear leveling (WL) ofNVM 239 locally with a local WL controller 219. The local WL controller219 may be implemented in software (i.e., firmware) and/or hardware.Each local WL controller 219 is configured to ensure usage of physicalnon-volatile memory of respective NVM device 237 is as even as possible.The local WL controller 219 operates on physical block addresses of eachrespective NVM device. Additionally, the control interface 238 is alsoconfigured for managing bad block (BB) relocation to make sure each ofthe physical NVM devices 237 will have a even wear level count tomaximize usage. Moreover, the control interface 238 is also configuredfor handing Error Code Correction (ECC) of corrupted data bits occurredduring NVM read/write operations hence further ensuring reliability ofthe NVMD devices 237. NVM 239 may include, but not necessarily limitedto, single-level cell flash memory (SLC), multi-level cell flash memory(MLC), phase-change memory (PCM), Magnetoresistive random access memory,Ferroelectric random access memory, Nano random access memory. For PCM,local wear level controller 219 does not need to manage wear level butother functions such as ECC and bad block relocation instead.

Each of the at least one intelligent NVM controller 231 includes acontroller logic 232 and a channel interface 233. Intelligent NVMcontrollers 231 are coupled to the internal bus 230 in parallel. Thevolatile memory buffer 220, also coupled to the internal bus, maycomprise synchronous dynamic random access memory (SDRAM). Data transferbetween the volatile memory buffer 220 and the non-volatile memorydevice 237 can be performed via direction memory access (DMA) via theinternal bus 230 and the intelligent NVM device controller 231. Volatilememory buffer 220 is controlled by volatile memory buffer controller222. PLL circuit 228 is configured for generating a timing signal forthe volatile memory buffer 220 (e.g., a SDRAM clock). The hub timingcontroller 224 together with data dispatcher 215 is configured fordispatching commands and sending relevant timing signals to the at leastone intelligent NVM device controller 231 to enable parallel datatransfer operations. For example, parallel advanced technologyattachment (PATA) signals may be sent over the internal bus 230 todifferent ones of the intelligent NVM device controllers 231. One NVMdevice controller 231 can process one of the PATA requests, whileanother NVM device processes another PATA request. Thus multipleintelligent NVM devices 237 are accessed in parallel.

CPU 226 is configured for controlling overall data transfer operationsof the first NVM based storage system 210 a. The local memory buffer 227(e.g., static random access memory) may be configured as data and/oraddress buffer to enable faster CPU execution. The storage protocolinterface bridge 214 is configured for sending and/or receivingcommands, addresses and data from a host computer via an externalstorage interface bus 213 (e.g., interface bus 113 of FIG. 1A or FIG.1B). Examples of the host computer (not shown) may be a personalcomputer, a server, a consumer electronic device, etc. The externalstorage interface bus 213 may include a Peripheral ComponentInterconnect Express (PCI-E) bus.

Finally, in order to increase security of data stored in the storagesystem 210 a, stored data may be encrypted using a dataencryption/decryption engine 223. In one embodiment, the dataencryption/decryption engine 223 is implemented basing on AdvancedEncryption Standard (AES), for example, a 128-bit AES.

FIG. 2B shows a second exemplary NVM based storage system 210 b inaccordance with another embodiment of the present invention. The secondNVM based storage system 210 b is an alternative to the first storagesystem 210 a. Instead of a generic volatile memory buffer 220, a doubledata rate synchronous dynamic random access memory (DDR SDRAM) buffer221 is used. Accordingly, a DDR SDRAM buffer controller 223 is used forcontrolling the DDR SDRAM buffer 221 and PLL circuit 228 to controlgeneration DDR SDRAM clock signals in the second exemplary NVM basedstorage system 210 b. Each of the intelligent NVM device controllers 231contains a DDR channel interface 234. Interface 236 between theintelligent NVM device 237 and corresponding controller 231 is based onDDR-NVM. Additionally, a PLL 240 is located within the intelligent NVMD237 to generate signals for DDR-NVM 239.

FIGS. 2C and 2D show third and fourth NVM based storage systems,respectively. The third storage system 210 c is an alternative to thefirst storage system 210 a without a volatile memory buffer 220, andassociated volatile memory controller 222 and PLL circuit 228. Thefourth storage system 210 d is an alternative to the second storagesystem 210 b without the DDR SDRAM buffer 221, DDR SDRAM buffercontroller 223 and PLL circuit 228.

FIG. 2E-1 is a diagram showing block access interlock signals 235Abetween a block access interface controller 233A in an intelligent NVMdevice controller 231A and a block access control interface 238A in theintelligent NVM device 237A of the NVM based storage system 210 a ofFIG. 2A. The block access interlock signals 235A includes a main clock(CLK), 8-bit data (DQ[7:0]), a card selection signal (CS), command(CMD), and a pair of serial control signals (Tx+/Tx− and Rx+/Rx−). Theserial control signals are configured to supply different voltages suchthat the differences of the voltages can be used for transmitting data.Transmitting signals (Tx+/Tx−) are from the intelligent NVM devicecontroller 231A to the intelligent NVM device 237A, while receivingsignals (Rx+/Rx−) are in the reverse direction from the intelligent NVMdevice 237B to the intelligent NVM device controller 231B.

Details of synchronous DDR interlock signals 236A are shown in FIG.2E-2. In the exemplary NVM based storage system 210 b of FIG. 2B, theintelligent NVM device controller 231B communicates with the intelligentNVM device 237B synchronous DDR interlock signals as follows: main clocksignal (CLK), data (e.g., 8-bit data denoted as DQ[7:0]), data strobesignal (DQS), chip enable signal (CE#), read-write indication signal(W/R#) and address latch enable (ALE)/command latch enable (CLE) signal.Main clock signal is used as a reference for the timing of commands suchas read and write operations, including address and control signals. DQSis used as a reference to latch input data into the memory and outputdata into an external device.

FIG. 2F is a diagram showing details of the DDR channel controller 234in the NVM based storage system 210 b of FIG. 2B. The DDR channelcontroller 234 comprises a chip selection control 241, a read/writecommand register 242, an address register 243, a command/address timinggenerator 244, a main clock control circuit 245, a sector input buffer251, a sector output buffer 252, a DQS generator 254, a readfirst-in-first-out (FIFO) buffer 246, a write FIFO 247, a data driver249 and a data receiver 250.

The chip selection control 241 is configured for generating chip enablesignals (e.g., CE0#, CE1#, etc.), each enables a particular chip thatthe DDR channel controller 234 controls. For example, multiple NVMdevices controlled by the DDR channel controller 234 include a pluralityof NVM chips or integrated circuits. The DDR channel controller 234activates a particular one of them at any one time. The read/writecommand register 242 is configured for generating read or write signalto control either a read or write data transfer operation. The addressregister 243 comprises a row and column address. The command/addresstiming generator 244 is configured for generating address latch enable(ALE) and command latch enable (CLE) signals. The clock control circuit245 is configured to generating a main clock signal (CLK) for the entireDDR channel controller 234. The sector input buffer 251 and the sectoroutput buffer 252 are configured to hold data to be transmitted in andout of the DDR channel controller 234. DQS generator 254 is configuredto generating timing signals such that data input and output are latchedat a different faster data rate than the main clock cycles. The readFIFO 246 and write FIFO 247 are buffers configured in conjunction withthe sector input/output buffer. The driver 249 and the receiver 250 areconfigured to send and to receive data, respectively.

FIG. 2G is a diagram showing the DDR control interface 238 and NVM 239in the NVM based storage system 210 b of FIG. 2B. The DDR controlinterface 238 receives signals such as CLK, ALE, CLE, CE#, W/R#, DQS anddata (e.g., DataIO or DQ[7:0]) in a command and control logic 276.Logical addresses received are mapped to physical addresses of the NVM239 in the command and control logic 276 based on a mapping table (L2P)277. The physical address comprises a column and row addresses that areseparately processed by a column address latch 271 and a row addresslatch 273. Column address is decoded in a column address decoder 272.Row address includes two portions that are decoded by a bank decoder 275and a row decoder 274. The decoded addresses are then sent toinput/output register 281 and transceiver 282 of the NVM 239. Actualdata are saved into page registers 283 a-b before being moved intoappropriate data blocks 284 a-b of selected banks or planes (e.g., Bank1, 2, etc.).

Referring now to FIG. 2H, which is a flowchart illustrating an exemplaryprocess 285 of encrypting plain text data using an dataencryption/decryption engine 223 based on 128-bit Advanced EncryptionStandard (AES) in accordance with one embodiment of the presentinvention. Process 285 may be implemented in software, hardware or acombination of both.

Process 285 starts at an ‘IDLE’ state until the dataencryption/decryption engine 223 receives plain text data (i.e.,unencrypted data) at step 286. Next, at step 287, process 285 groupsreceived data into 128-bit blocks (i.e., states) with each blockcontaining sixteen bytes or sixteen (16) 8-bit data arranged in a 4×4matrix (i.e., 4 rows and 4 columns of 8-bit data). Data padding is usedfor ensuring a full 128-bit data. At step 288, a cipher key is generatedfrom a password (e.g., user entered password).

At step 289, a counter (i.e., Round count) is set to one. At step 289,process 285 performs an ‘AddRoundKey’ operation, in which each byte ofthe state is combined with the round key. Each round key is is derivedfrom the cipher key using the key schedule (e.g., Rjindael's keyschedule). Next, at step 291, process 285 performs a ‘SubBytes’operation (i.e., a non-linear substitution step), in which each byte isreplaced with another according to a lookup table (i.e., the RijndaelS-box). The S-box is derived from the multiplicative inverse over GaloisField GF(2⁸). To avoid attacks based on simple algebraic properties, theS-box is constructed by combining the inverse function with aninvertible affine transformation. The S-box is also chosen to avoid anyfixed point (and so is a derangement), and also any opposite fixedpoints.

At step 292, next operation performed by process 285 is called‘ShiftRows’. This is a transposition step where each row of the state isshifted cyclically a certain number of steps. For AES, the first row isleft unchanged. Each byte of the second row is shifted one to the left.Similarly, the third and fourth rows are shifted by offsets of two andthree respectively. For the block of size 128 bits and 192 bits theshifting pattern is the same. In this way, each column of the outputstate of the ShiftRows step is composed of bytes from each column of theinput state. (Rijndael variants with a larger block size have slightlydifferent offsets). In the case of the 256-bit block, the first row isunchanged and the shifting for second, third and fourth row is 1 byte, 2bytes and 3 bytes respectively—although this change only applies for theRijndael cipher when used with a 256-bit block, which is not used forAES.

Process 285 then moves to decision 293, it is determined if the counterhas reached ten (10). If ‘no’, process 285 performs ‘MixColumns’operation at step 294. This step is a mixing operation which operates onthe columns of the state, combining the four bytes in each column. Thefour bytes of each column of the state are combined using an invertiblelinear transformation. The MixColumns function takes four bytes as inputand outputs four bytes, where each input byte affects all four outputbytes. Together with ShiftRows, MixColumns provides diffusion in thecipher. Each column is treated as a polynomial over GF(2⁸) and is thenmultiplied modulo x⁴+1 with a fixed polynomial c(x)=3x³+x²+x+2. TheMixColumns step can also be viewed as a multiplication by a particularmaximum distance separable (MDS) matrix in Rijndael's finite field. Thecounter is then incremented by one (1) at step 295 before moving back tostep 290 for another round.

When the counter ‘Round count’ is determined to be 10 at decision 293,process 285 sends out the encrypted data (i.e., cipher text) beforegoing back to the ‘IDLE’ state for more data. It is possible to speed upexecution of the process 285 by combining ‘SubBytes’ and ‘ShiftRows’with ‘MixColumns’, and transforming them into a sequence of tablelookups.

FIG. 3 is a block diagram illustrating salient components of anexemplary dual-mode NVM based storage device. The dual-mode NVM basedstorage device 300 connects to a host via a storage interface 311 (e.g.,Universal Serial Bus (USB) interface) through upstream interface 314.The storage system 300 connects to intelligent NVM devices 337 throughSSD downstream interfaces 328 and intelligent NVM device controller 331.The interfaces provide physical signaling, such as driving and receivingdifferential signals on differential data lines of storage interfaces,detecting or generating packet start or stop patterns, checking orgenerating checksums, and higher-level functions such as inserting orextracting device addresses and packet types and commands.

Hub timing controller 316 activates the storage system 300. Data isbuffered across storage protocol bridge 321 from the host to NVM devices337. Internal bus 325 allows data to flow among storage protocol bridge321 and SSD downstream interfaces 328. The host and the endpoint mayoperate at the same speed (e.g., USB low speed (LS), full speed (FS), orhigh-speed (HS)), or at different speeds. Buffers in storage protocolbridge 321 can store the data. Storage packet preprocessor 323 isconfigured to process the received data packets.

When operating in single-endpoint mode, transaction manager 322 not onlybuffers data using storage protocol bridge 321, but can also re-orderpackets for transactions from the host. A transaction may have severalpackets, such as an initial token packet to start a memory read, a datapacket from the memory device back to the host, and a handshake packetto end the transaction. Rather than have all packets for a firsttransaction complete before the next transaction begins, packets for thenext transaction can be re-ordered by the storage system 300 and sent tothe memory devices before completion of the first transaction. Thisallows more time for memory access to occur for the next transaction.Transactions are thus overlapped by re-ordering packets.

Transaction manager 322 may overlap and interleave transactions todifferent flash storage blocks, allowing for improved data throughput.For example, packets for several incoming transactions from the host arestored in storage protocol bridge 321 or associated buffer (not shown).Transaction manager 322 examines these buffered transactions and packetsand re-orders the packets before sending them over internal bus 325 tothe NVM devices 337.

A packet to begin a memory read of a flash block through a firstdownstream interface 328 a may be reordered ahead of a packet ending aread of another flash block through a second downstream interface 328 bto allow access to begin earlier for the second flash block.

FIG. 4A is a diagram showing a first exemplary intelligent non-volatilememory (NVM) device controller for single channel intelligent NVMD arrayin accordance with one embodiment of the present invention. The firstNVM device controller comprises a processor 412 that controls two NVMcontroller interfaces: odd interface 416 a and even interface 416 b, anda clock source 417. Each of the two NVM controller interfaces sendsseparate card selection signal (e.g., CS#1, CS#2) and logical address(e.g., LBA) to respective intelligent NVM device 424 a-b under control.Clock source 417 is configured to send out a single timing signal (e.g.,CLK_SYNC) in a single channel to all of the intelligent NVM devices 424a-b. Each of the intelligent NVM devices 424 a-b contains a controlinterface 426 and a NVM 428 (part of the NVM array).

FIG. 4B is a diagram showing a second exemplary intelligent non-volatilememory (NVM) device controller for multiple channel interleavedintelligent NVMD array in accordance with one embodiment of the presentinvention. The second intelligent NVM device controller comprises aprocessor 432 that controls two NVM controller interfaces (odd 436 a andeven 436 b) and two separate clock sources (odd 438 a and even 438 b).Each of the NVM controller interfaces 436 controls at least twointelligent NVM devices 424, for example, odd NVM controller interface436 a controls intelligent NVM devices #1 424 a and #3 424 c using atiming signal (CLK_SYNC_ODD) from the odd clock source 438 a. Becausethere are at least two NVM devices 424 controlled by each of the NVMcontroller interfaces 436, data transfer operations to the at least twoNVM device can be performed with an interleaved addressing scheme withhigher efficiency thereby achieving high performance.

Logical address space (LAS) 500 in a host computer is shown in the leftcolumn of FIG. 5A. LAS 500 is partitioned into three areas: system filearea 501, user data file area 507 and cache area 517. Examples of filesin the system file area 501 are master boot record (MBR) 502, initialprogram loader 504 and file allocation table (FAT) 506. In the user datafile area 507, directory information 508, user data files 512 a-b anduser data file cluster chain 514 are exemplary files. Finally user dataimage stored in a cache memory 518 is used for improving systemperformance.

Physical address space (PAS) 540 in a non-volatile memory device isshown in the right column of FIG. 5A. PAS 540 is partitioned into fourareas: system file area 541, relocatable system file area 547, user datafile area 551 and reserved area 561. The system file area 541 containsfiles such as MBR 542, initial program loader 544 and initial FAT 546.The relocatable system file area 547 may contain FAT extension 548. Theuser data file area 551 includes directory information 552, user datafiles 553 a-b, and user data cluster chains 554. The reserved area 561may include partial data file linkage 562, reserved area for bad block(BB) 564 and a reserved area for storing volatile memory buffer 566 inan emergency. The reserved area for storing volatile memory buffer 566is configured for holding data from the volatile memory buffer whenunexpected power failure occurs, for example, last block of thenon-volatile memory device may be designated. In one embodiment, thelast block has an address of ‘0xFFFF0000’.

Volatile memory buffer 520 is partitioned into two portions: pagebuffers 521 and command (CMD) queue 530. The page buffers 521 areconfigured for holding data to be transmitted between the host and theNVM device, while the command queue 530 is configured to store receivedcommands from the host computer. The size of a page buffer is configuredto match page size of physical NVM, for example, 2,048-byte for MLCflash. In addition, each page would require additional bytes for errorcorrection code (ECC). The command area 530 is configured to hold Ncommands, where N is a whole number (e.g., positive integer). Thecommand queue 530 is so sized that stored commands and associated datacan be flushed or dumped to the reserved area 566 using reservedelectric energy stored in a designated capacitor of the NVM basedstorage system. In a normal data transfer operation, data stored intoNVM device must be mapped from LAS 500 to PAS 540. However, in anemergency situation, such as upon detecting an unexpected power failure,data transfer (i.e., flushing or dumping data from volatile memorybuffer to reserved area) is performed without any address mapping ortranslation. Goal is to capture perishable data from volatile memoryinto non-volatile memory so that data can be later recovered.

FIG. 5B shows details of L2P table 277 configured for mapping LAS 500 toPAS 540 inside the intelligent NVM device (NVMD) 238. The LAS to PASmapping is a one-to-one relationship. When a bad block (BB) isencountered, a new block must be allocated before any data transfer canbe performed to the NVMD 238.

One advantage of using volatile memory buffer is to allow data writecommands with overlapped target addresses to be merged before writing tothe NVMD. Merging write commands can eliminate repeated data programmingto same area of the NVM thereby increasing endurance of the NVMD. FIG.5C is an example demonstrating how to merge data write commands involatile memory buffer. There are two commands, ‘command queue #1’ 570 aand ‘command queue #m’ 570 b, stored in the command queue of thevolatile memory buffer. Each of the command queues 570 comprisesfollowing fields: command identifier 571 a, start address 572 a, numberof sectors to be transferred 573 a and physical data for the number ofsectors 574 a-579 a.

Shown in FIG. 5C, ‘command queue #1’ 570 a contains four data sectors tobe transferred starting from address ‘addr1’ 574 a. As a result, pagebuffer 580 contains data at ‘addr1’ 574 a, ‘addr2’ 575 a, ‘addr3’ 576 aand ‘addr4’ 577 a from ‘command queue #1’ 570 a. ‘command queue #m’ 570b also contains four data sectors to be transferred, but starting fromaddress ‘addr2’ 575 b.

Shown in the bottom row of FIG. 5C, page buffer 580 contains data at thefollowing five data sectors at ‘addr1’ 574 a, ‘addr2’ 575 b, ‘addr3’ 576b, ‘addr4’ 577 b and ‘add5’ 578 b as a result of merged data from thesetwo commands. These means that the merging of these two write commandsin volatile memory eliminate programming the NVM device for thoseoverlapped area.

FIG. 6A is a first timeline 600 showing time required to perform anormal data programming operation of one data page to the NVM devicewithout volatile memory buffer support. The timeline 600 contains threeportions: 1) LAS to PAS translation time 602; 2) writing one data pageto the NVM device 604; and 3) time to notify the host with an‘end-of-transfer’ (EOT) signal 606. The ‘EOT’ is used for notifying thehost that the data transfer operation has been completed.

FIG. 6B is a second timeline 610, which is similar to the first timelineof FIG. 6A. The difference is that a bad block is encountered duringdata transfer. The second timeline 610 contains four parts: 1) LAS toPAS translation time 602; 2) allocating a new data block to replace thebad block encountered 603; 3) writing one data page to the NVM device604; and 4) time to notify the host with an ‘end-of-transfer’ (EOT)signal 606.

FIG. 6C is a third timeline 620 showing normal data transfer operationin a NVM based storage system with a volatile memory buffer support. Thethird timeline 620 contains a number of burst writes (e.g., threewrites) in the volatile memory buffer and time to write back those datato the NVM device. Each of the burst writes contains two parts: 1) timefor one burst write cycle in the volatile memory 622; and 2) time tonotify the host with an ‘end-of-transfer’ (EOT) signal 626. When pagebuffers or command queue are full, the data needs to be written orprogrammed to the NVM device. The write back time includes twoportions: 1) time for mapping LAS to PAS and updating L2P table 627 and2) time for actually programming the NVM device 628.

FIG. 6D is a fourth timeline 630 showing emergency data transferoperation in a NVM based storage system upon detecting an unexpectedpower failure. In the fourth timeline 630, the third burst write cycleis interrupted by an unexpected power failure 637. Upon detecting suchpower failure, up to maximum N commands and associated data stored inthe command queue of the volatile memory buffer are dumped or flushed toreserved area of the NVM device right away (shown in 638). Due to thenature of urgency and due to the limited reserved electric energy storedin a capacitor, no address mapping is performed. The data are copied tothe reserved area of the NVM device without any modification. Uponrestart of the storage system, stored data in the reserved area is usedfor restoring the volatile memory buffer before resuming normaloperation of the storage system.

Referring now to FIGS. 7A-7B, which are collectively a flowchartillustrating an exemplary process 700 of a data transfer operation of aNVM based storage system 210 b of FIG. 2B in accordance with oneembodiment of the present invention. The process 700 may be implementedin software, hardware or a combination of both.

Starting at an ‘IDLE’ state until the NVM based storage system 210 b hasreceived data transfer command from a host computer via a storageinterface at step 702. Next, at decision 704, it is determined whetherthe received command is a data write command, if ‘yes’, the storagesystem 210 b extracts logical address (e.g., LBA) from the receivedcommand at step 706. Then, process 700 moves to decision 708, it isdetermined whether the logical address is located in the system area. If‘yes’, system files (e.g., MBR, FAT, Initial program loader, etc.) aresaved to the NVM device right away at step 710 and process 700 goes backto the ‘IDLE’ state for another command.

If ‘no’, process 700 moves to decision 712. It is determined whetherdata transfer range in the received command is fresh or new in thevolatile memory buffer. If ‘no’, existing data at overlapped addressesin the page buffers is overwritten with the new data at step 714.Otherwise, data is written into appropriate empty page buffers at step716. After the data write command has been stored in the command queuewith data stored in the page buffers, an ‘end-of-transfer’ signal issent back to the host computer at 718. Process 700 moves back to the‘IDLE’ state thereafter.

Referring back to decision 704, if ‘no’, process 700 moves to step 722by extracting logical address from the received data read command. Next,at decision 724, it is determined whether data transfer range exists inthe volatile memory buffer. If ‘no’, process 700 triggers NVM readcycles to retrieve requested data from NVM device at step 726.Otherwise, requested data can be fetched directly from the volatilememory buffer without accessing the NVM device at step 728. Next, atstep 730, requested data are filled into the page buffers beforenotifying the host computer at step 730. Finally, process 700 moves backto the ‘IDLE’ state for another data transfer command. It is noted thatthe data transfer range is determined by the start address and thenumber of data sectors to be transferred in each command.

FIG. 8 is a flowchart showing an exemplary process 800 of using avolatile memory buffer in the NVM based storage system 210 b of FIG. 2B,according to an embodiment of the present invention. Process 800 startsin an ‘IDLE’ state until a data transfer command has been received inthe NVM based storage system 210 b at step 802. Next, at step 804, thereceived command is stored in the command queue of the volatile memorybuffer. Process 800 then moves to decision 806 to determine whether thereceived command is a data write command. If ‘yes’, at step 808, datatransfer range is extracted from the received command. Next, at step810, command with overlapped target addresses is merged in the pagebuffers. Finally, data is written to the NVM device from the pagebuffers at step 812.

Referring back to decision 806, if ‘no’, data range is extracted fromreceived command at step 818. Next, process 800 moves to decision 820 todetermine whether the data range exists in the volatile memory buffer.If ‘no’, the process 800 fetches requested data from the NVM device atstep 824, otherwise the data is fetched from the volatile memory bufferat step 822. Process 800 ends thereafter.

FIG. 9 is a flowchart illustrating an exemplary process 900 ofperforming direct memory access (DMA) operation in the NVM based storagesystem 210 b of FIG. 2B, according to an embodiment of the presentinvention. Process 900 receives data transfer command from a hostcomputer and stores into the command queue at step 902. This continuesuntil the command queue is full, which is determined in decision 904.Next, at step 906, data transfer range is setup by extracting startingaddress and number of data sectors to be transferred in the receivedcommand. At step 908, the storage system 210 b starts DMA action. Thestorage system 210 b fetches data to page buffers at step 910. Process900 moves to decision 912, it is determined whether the NVM device is anintelligent NVM device that can handle LAS to PAS mapping. If ‘no’,process 900 performs raw NVM data transfer at step 914. Otherwise,process 900 triggers NVM programming cycles to store data from the pagebuffers at step 916. Finally, process 900 moves to decision 918 todetermine whether there are more commands in the command queue. If ‘yes’process 900 goes back to step 916, otherwise DMA and process 900 ends.

FIG. 10 a flowchart illustrating a first exemplary process 1000 afterunexpected power failure has been detected in the NVM based storagesystem 210 b of FIG. 2B, according to an embodiment of the presentinvention. Process 1000 starts by performing data transfer commandsreceived from a host computer at step 1002. An ‘EOT’ signal is sent backto the host computer when the data write operation has completed in thevolatile memory buffer. In the meantime, the storage system 210 bmonitors unexpected power failure at decision 1006. If ‘no’, process1000 goes on in normal operation. Otherwise, at step 1008, process 1000suspends or aborts current on-going data write operation without sending‘EOT’ signal. Then, process 1000 starts an emergency power-downprocedure by performing burst write back all of the previous stored datasectors in the page buffers already issued ‘EOT’ signal to the hostcomputer, to the reserved area of the NVM device at step 1008. Process1000 ends thereafter.

FIG. 11 is a flowchart illustrating a second exemplary process 1100after detecting a power failure in the NVM based storage system 210 b ofFIG. 2B, according to an embodiment of the present invention. Process1100 starts at an ‘IDLE’ state until the storage system has detected andreceived a power failure signal at step 1102. Next, at step 1104,process 1100 suspends or aborts current cycle in the volatile memorybuffer. Then, at step 1106, process 1100 dumps or flushes all storeddata that have issued ‘EOT’ signal to the reserved area of the NVMdevice one data page at a time. Decision 1108 determines whetheradditional data needs to be flushed. If ‘yes’, process 1100 goes back tostep 1106 until no more data and process 1100 ends thereafter.

FIG. 12 is a flowchart illustrating an exemplary process 1200 ofrecovering of the NVM based storage system 210 b of FIG. 2B afterunexpected power failure, according to an embodiment of the presentinvention. Process 1200 starts at an ‘IDLE’ state until the storagesystem 210 b receives a diagnosis command indicating abnormal filelinkage upon power-on of the storage system 210 b from a host computerat step 1202. Next, at step 1204, process 1200 restores the volatilememory buffer by copying data stored in the reserved area (e.g., lastdata block) of the NVM device to the volatile memory buffer. Uponsuccessful restoration of the volatile memory buffer, process 1200erases the stored data in the reserved area of the NVM device at step1206. This is to ensure that the reserved area is ready for nextemergency data transfer operation. Finally, at step 1208, process 1200notifies the host computer that the NVM based storage system 210 b isready to operate in normal condition. Process 1200 moves back to the‘IDLE’ state thereafter.

FIGS. 13A-13B are first and second waveform diagrams showing timerequired for performing data write operation from the volatile memorybuffer to the intelligent NVM device in the first NVM based storagesystem 210 a and the second NVM based storage system 210 b,respectively.

In the first waveform diagram of FIG. 13A, chip select (CS#) is pulsedlow in sync with either row address strobe (RAS#) or column addressstrobe (CAS#). Read/write indicator (W/R#) activates mux'ed address at‘row 1’ and ‘row 2’. As a result, ‘data 1’ and ‘data 2’ output fromvolatile memory are shown with burst data read. After the data have beenread, ECC generation is followed before saving to page buffers. Finallythe NVM write sequence can start.

The second waveform diagram of FIG. 13B is similar to the first one. Thedifference is an additional DQS signal is used for burst read operationof DDR SDRAM. A different clock cycle (DQS) faster than main systemclock (CLK) is used for data read operation, hence achieving a fasterdata access to and from the NVM device. Using DDR SDRAM as volatilememory buffer increases performance of the NVM based storage system.

Some portions of the preceding detailed descriptions have been presentedin terms of algorithms and symbolic representations of operations ondata bits within a computer memory. These algorithmic descriptions andrepresentations are the ways used by those skilled in the dataprocessing arts to most effectively convey the substance of their workto others skilled in the art. An algorithm is here, and generally,conceived to be a self-consistent sequence of operations leading to adesired result. The operations are those requiring physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, transferred, combined, compared, and otherwisemanipulated. It has proven convenient at times, principally for reasonsof common usage, to refer to these signals as bits, values, elements,symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. Unlessspecifically stated otherwise as apparent from the above discussion, itis appreciated that throughout the description, discussions utilizingterms such as “processing” or “computing” or “calculating” or“determining” or “displaying” or the like, refer to the action andprocesses of a computer system, or similar electronic computing device,that manipulates and transforms data represented as physical(electronic) quantities within the computer system's registers andmemories into other data similarly represented as physical quantitieswithin the computer system memories or registers or other suchinformation storage, transmission or display devices.

Embodiments of the present invention also relate to an apparatus forperforming the operations herein. This apparatus may be speciallyconstructed for the required purposes, or it may comprise ageneral-purpose computer selectively activated or reconfigured by acomputer program stored in the computer. Such a computer program may bestored in a computer readable medium. A machine-readable medium includesany mechanism for storing or transmitting information in a form readableby a machine (e.g., a computer). For example, a machine-readable (e.g.,computer-readable) medium includes a machine (e.g., a computer) readablestorage medium (e.g., read only memory (“ROM”), random access memory(“RAM”), magnetic disk storage media, optical storage media, flashmemory devices, etc.), etc.

The algorithms and displays presented herein are not inherently relatedto any particular computer or other apparatus. Various general-purposesystems may be used with programs in accordance with the teachingsherein, or it may prove convenient to construct more specializedapparatus to perform the required method operations. The requiredstructure for a variety of these systems will appear from thedescription below. In addition, embodiments of the present invention arenot described with reference to any particular programming language. Itwill be appreciated that a variety of programming languages may be usedto implement the teachings of embodiments of the invention as describedherein.

Although the present invention has been described with reference tospecific embodiments thereof, these embodiments are merely illustrative,and not restrictive of, the present invention. Various modifications orchanges to the specifically disclosed exemplary embodiments will besuggested to persons skilled in the art. For example, whereas DDR SDRAMhas been shown and described to be used in volatile memory buffer, othervolatile memories suitable to achieve the same functionality may beused, for example, SDRAM, DDR2, DDR3, DDR4, Dynamic RAM, Static RAM.Additionally, whereas external storage interface has been described andshown as PCI-E, other equivalent interfaces may be used, for example,Advance Technology Attachment (ATA), Serial ATA (SATA), Small ComputerSystem Interface (SCSI), Universal Serial Bus (USB), ExpressCard, fiberchannel Interface, optical connection interface circuit, etc.Furthermore, whereas data security feature has been shown and describedusing a 128-bit AES, other equivalent or more secured standards may beused, for example, 256-bit AES. Finally, the NVM device has been shownand described to comprise two or four device, other numbers of NVM maybe used, for example, 8, 16, 32 or any higher numbers that can bemanaged by embodiments of the present invention. In summary, the scopeof the invention should not be restricted to the specific exemplaryembodiments disclosed herein, and all modifications that are readilysuggested to those of ordinary skill in the art should be includedwithin the spirit and purview of this application and scope of theappended claims.

1. A non-volatile memory (NVM) based storage system comprising: at leastone NVM device configured for providing data storage, wherein each ofthe at least one NVM device includes a control interface and at leastone NVM, the control interface is configured for receiving logicaladdresses, data, commands and timing signals, each of the logicaladdresses is extracted such that a corresponding physical address can bemapped into within said each of the control interface logic to performdata transfer operations, wherein the control interface further includesa wear leveling controller configured for managing wear level of the atleast one NVM; an internal bus; at least one NVM device controller,coupled to the internal bus, each configured for controllingcorresponding one of the at least one NVM device; a data dispatchertogether with the hub timing controller, configured for dispatchingcommands to one or more of the at least one NVM device controller; acentral processing unit (CPU), coupled to the data dispatcher,configured for control overall data transfer operations of the NVM basedstorage system; and a storage protocol interface bridge, coupled to thedata dispatcher, configured for receiving data transfer commands from ahost computer via external storage interface.
 2. The system of claim 1,further comprises a hub timing controller and a volatile memory buffer,coupled to the internal bus, wherein the hub timing controller isconfigured for providing timing to said each of the at least one NVMdevice and the volatile memory buffer is controlled by a volatile memorybuffer controller.
 3. The system of claim 2, further comprises aphase-locked loop circuit, coupled to the CPU, configured for providingtiming clock to the volatile memory buffer.
 4. The system of claim 2,wherein the volatile memory buffer is partitioned into a command queuearea and a plurality of page buffers.
 5. The system of claim 4, whereinthe command queue is configured for storing received commands from thehost computer by the storage protocol interface bridge.
 6. The system ofclaim 4, wherein the plurality of page buffers is configured to holdtransition data to be transmitted between the host computer and the atleast one NVM device.
 7. The system of claim 4, wherein the volatilememory buffer is configured to allow data write commands with overlappedtarget addresses to be merged before writing to the at least one NVMdevice.
 8. The system of claim 4, wherein the volatile memory buffer isconfigured to preload data to anticipate requested data in data readcommands.
 9. The system of claim 4, wherein the at least one NVM deviceis partitioned to have a reserved area configured for storing commandsand associated data in the volatile memory buffer after an unexpectedpower failure has been detected.
 10. The system of claim 9, wherein thecommand queue is so sized such that the commands stored therein can becopied to the reserved area using reserved electric energy stored in adesignated capacitor of the NVM based storage system.
 11. The system ofclaim 2, wherein the volatile memory buffer comprises double data ratesynchronous dynamic random access memory.
 12. The system of claim 1,wherein the at least one NVM device controller are connected to aplurality of data channels such that parallel data transfer operationsusing interleaved memory addresses can be conducted, each of the datachannels connects to at least two of the NVM devices.
 13. The system ofclaim 1, further comprises a data encryption/decryption engine, coupledto the internal bus, configured for providing data security based onAdvanced Encryption Standard.
 14. A method of performing data transferoperations in a non-volatile memory (NVM) based storage system with avolatile memory buffer comprising: receiving a data transfer commandfrom a host computer via an external storage interface; extracting adata transfer range from the received command; when the received commandis data read command and the data transfer range is found in thevolatile memory buffer, fetching requested data from the volatile memorybuffer to one or more page buffers before notifying the host computer,wherein the one or more page buffers are configured in the volatilememory buffer; when the received command is data read command and thedata transfer range is not found in the volatile memory buffer,triggering read cycles to retrieve the requested data from at least onenon-volatile memory device to the one or more page buffers beforenotifying the host computer; when the received command is data writecommand and a command queue is not full, storing the received command inthe command queue, wherein the command queue is configured in thevolatile memory buffer; when the received command is data write commandand the command queue is full, and the data transfer range is found inthe volatile memory buffer, updating corresponding data in the one ormore page buffers before writing to the at least one non-volatile memorydevice; when the received command is data write command and the commandqueue is full, and the data transfer range is not found in the volatilememory buffer, triggering write cycles to store data to the one or morepage buffers in the volatile memory buffer before writing to the atleast one non-volatile memory device; whereby the data in the one ormore page buffers can be updated without writing to the at least onenon-volatile memory device and the data in the one or more page bufferscan be preloaded for anticipating data reading operation.
 15. The methodof claim 14, further comprises sending an end-of-transaction signal tothe host computer after the received command has been completely storedin the command queue.
 16. The method of claim 15, further comprisesmonitoring unexpected power failure of the NVM based storage system suchthat enough time is preserved for storing perishable data in a volatilememory buffer to ensure data integrity of the NVM based storage system.17. The method of claim 16, further comprises predefining a reservedarea in the at least one NVM device configured for storing commands anddata in the volatile memory buffer after the unexpected power failurehas been detected.
 18. The method of claim 17, further comprises storingall of the stored commands that have been issued the end-of-transactionsignal to the host computer, into the reserved area of the at least onenon-volatile memory without performing logical-to-physical addressconversion.
 19. The method of claim 17, further comprises storing all ofthe stored commands that have been issued the end-of-transaction signalto the host computer, into the reserved area of the at least onenon-volatile memory without performing logical-to-physical addressconversion.
 20. A method of initializing a non-volatile memory (NVM)based storage system with a volatile memory buffer comprising: receivinga ‘recover-from-unexpected-power-failure’ command from a host computerupon powering on the NVM based storage system after an unexpected powerfailure; restoring volatile memory buffer by copying stored data from areserved area of at least one non-volatile memory device, wherein thevolatile memory buffer is configured with a command queue, and one ormore page buffers; erasing the stored data from the reserved area uponcompletion of said restoring of the command queue and the data in theone or more page buffers; and notifying the host computer that the NVMbased storage system is in normal operating condition.
 21. The method ofclaim 20, wherein the reserved area comprises last physical block of theat least one non-volatile memory device.